Ferroelectric field-effect transistors have been considered for use in memory arrays in the form of non-volatile random access memory. For example, FIGS. 1A and 1B are schematic diagrams of a conventional memory array 100 including a plurality of FeFETs 110. In particular, the portion of the memory array 100 in FIG. 1A is the cross-section taken along line 1A of the top view shown in FIG. 1B. Each FeFET 110 includes a source region 112, a drain region 114, and a body region 116 (collectively referred to herein as an “FET structure”) formed over an insulating substrate 130. Each FeFET 110 may include a gate 118 separated from the FET structure by a ferroelectric material 120. In other words, at a very general level, a FeFET may have a similar structure to a conventional FET, with the gate oxide being replaced by the ferroelectric material 120. Each FeFET 110 may comprise a memory cell for the memory array 100.
The memory array 100 includes the plurality of two-dimensional (planar) arrangement of FeFETs 110 over the insulating substrate 130. Each FeFET 110 may comprise a memory cell for the memory array 100 to store a state to be interpreted as data. The state of the FeFET 110 may be based on the polarization of the ferroelectric material 120 that may be switched in the presence of an external field. For example, the ferroelectric material 120 may exhibit a positive polarization (which may be interpreted as a “1”) or a negative polarization (which may be interpreted as a “0”) for an individual FeFET 110. In operation, the FeFET 110 may receive a combination of voltages to contacts coupled to the gate 118, the source region 112, and the drain region 114 in order to write to, erase, or read the state of the FeFET 110.
During a read operation, current 102 may flow through the FeFET 110 from the source region 112 to the drain region 114 of the selected FeFET 110. The conventional memory array 100 may have source contacts and drain contacts (not shown) that are on the same side of the memory array 100. As a result, the current 102 may flow from a first end 150 of the memory array 100 through the FeFET 110 and then return to the same first end 150 of the memory array 100. As a result, the current path may have a different length depending on the position of the FeFET 110 in the memory array 100. For example, the current 102 may have a path that is shorter for a FeFET 110 that is proximate the first end 150 and longer for a FeFET 110 that is proximate a second end 152 of the memory array 100. As a result, the series resistance along the current path may not be uniform when accessing one FeFET 110 in comparison to the accessing another FeFET 110 in the memory array 100. In addition, the conventional memory array 100 configured in a two-dimensional architecture may have feature sizes that are undesirably large, and which may not enable a cell density that is practical for use.